Your cart is currently empty!
Objective: In this lab you will design a simple 4-bit ALU and analyse the efficiency in terms of processing delay and power consumption. Problem: In the previous labs you had already designed and analysed different 4-bit adders, subtractors and multipliers in Verilog. a) By choosing the best candidates from the…
Objective:
In this lab you will design a simple 4-bit ALU and analyse the efficiency in terms of processing delay and power consumption.
Problem:
In the previous labs you had already designed and analysed different 4-bit adders, subtractors and multipliers in Verilog.
Post-lab:
Submit a post-lab report with your verified outputs and performance analysis. All your submissions should be clear and concise.
Copied and late submissions will not be evaluated.