In this section you will implement the multiplier speci ed in pset 3 problem 2, except with 8-bit values instead of 4.
2.1(a). Create a declarative Verilog module to generate the lowest order partial product given the current (shifted) values of A and B as in pset 3 problem 2.0(a). Include a propagation delay of #1.
2.1(b). Create a declarative Verilog module to generate a one-bit output given an appropriate input as in pset 3 problem 2.0(c). Include a propagation delay of #4.
2.1(c). Using the above two modules, as well as the other modules provided, generate the structural Verilog imple-menting the multiplier as in pset 3 problem 2.0(e).
2.1(d). Set the clock period appropriately to ensure the dynamic discipline is met. Assume a setup time of #6 for the D-register. (You can assume the contamination delay meets the hold time requirements.)
2.2 Input de-serializer
In this section, you will create the module that takes in a 1 bit time series indicating the Morse code pulses as in Fig. 2, and generates a set of four 8-bit values measuring the pulse widths of the most recent Morse code letter.
2.2(a). Using any combination of structural and declarative statements, write a Verilog module that implements a counter to measure the width of an incoming pulse (1 value on the input bitstream) or gap (0 value on the input bitstream) in clock ticks as an 8-bit value. Output the following four values:
the 8-bit width of the most recent completed pulse or gap,
a one bit value indicating whether that width is short or long (the di erence between short and long will be set as the Verilog macro THRESHOLD),
a one bit value indicating whether that width corresponds to a pulse (1) or gap (0), and a one bit ag that gets pulsed high for one clock cycle when a new width is ready.
2.2(b). Design a shift register module that stores and outputs four 8-bit values, with an 8-bit input value as well as one of the following input commands:
CLEAR: Reset all stored values to 8’b0.
LOAD: Shift the input value in to the lowest register, moving all stored values to the next higher registers.
HOLD: Do nothing.
Implement this using any combination of structural and declarative Verilog.
2.2(c). Design an FSM based on the outputs of your width-measurement module that generates the commands for your shift register module, as well as a one bit ag that gets pulsed high for one clock cycle when the pulse widths stored in the shift register represent a complete Morse code letter. Recall that pulses within a letter are separated by short gaps, while letters are separated by long gaps. Implement this using any combination of structural and declarative Verilog.
2.2(d). Connect the FSM, shift register, and width-measurement modules using structural Verilog to create your input deserializer.
2.H EE89 extra assignment
2.H(a). Using a counter, build a clock divider module to generate a 3Hz clock from the internal Basys3 100MHz clock. Display this clock on an LED.
2.H(b). Build a module to display the lowest 4 bits of each of four 8-bit values as a hex digit on the four 7-segment displays.
2.H(c). Synthesize the input de-serializer, using your 3Hz clock instead of the clock gen module. Connect the 1-bit input stream to a push-button on the board. Display the results of the de-serializer on the 7-segment displays using the above display module.