$35.00
Description
1 Objectives
The purpose of this lab is to characterize NPN and PNP bipolar junction transistors (BJT), and to analyze and design
DC biasing circuits to set the DC operating point of BJTs.
2 Introduction
Figure 1 shows typical symbols for the NPN and PNP BJTs. Depending on the applied DC bias, BJT has three regions of operation:
• Cutoff Region: If both base-emitter and base-collector junctions are reverse biased, the BJT enters the cutoff region. All terminal currents are extremely small, and the transistor is off.
• Active Region: The base-emitter junction is forward biased, and the base-collector junction is reverse biased to make a BJT operate in the active region. The active region is used to design a linear amplifier.
• Saturation Region: When both the base-emitter and base-collector junctions are forward biased, the BJT enters the saturation region.
C E
_{I}_{C } _{I}_{E}
I_{B } ^{V}EB
B
^{V}BE
^{V}CE
I_{E}
_{E}
^{B } ^{V}_{EC}
^{I}_{B}
^{I}_{C}
_{C}
(a) (b)
Figure 1: Bipolar junction transistor (BJT) (a) NPN (b) PNP
In the active region, the collector current (I_{C} ) of NPN and PNP devices are exponential functions of base-emitter voltage (V_{BE} ) and emitter-base voltage (V_{EB} ), respectively, given by
^{I}C ,npn ^{=} ^{I}S ^{e} ^{V}^{BE }^{/}^{V}^{T} ^{I}C ,pnp ^{=} ^{I}S ^{e} ^{V}^{EB} ^{/}^{V}^{T} ^{(1)}
where I_{S} is the saturation current and V_{T } is the thermal voltage, which is approximately 25mV at room temperature. For both NPN and PNP, the base current I_{B } is a small fraction of I_{C} , given by
_{I}_{C}
^{I}_{B } ^{=}
_{(2)}
^{β}
and the emitter current I_{E } is the sum of the base and collector currents, given by
_{I}_{C}
where
^{I}_{E } ^{=} ^{I}_{C } ^{+} ^{I}_{B } ^{=} ^{(β} ^{+} ^{1)}^{I}_{B} ^{=}
β α=
^{β} ^{+} ^{1}
_{(3)}
^{α}
(4)
βisknownasthecurrentgainofthetransistor,which variessignificantlywith temperature,anditcanbedifferent betweentwotransistorsofthesametype. Typicalvalue ofβisaround100,resulting inα=0.99.
c Department of Electrical and Computer Engineering, Texas A&M University
2.1 BJT Characterization
Figure 2shows acharacterizationcircuit foranNPN BJT.Toobtain I_{C } as a function of V_{BE} , V_{1} is swept while V_{2 }is kept constant, resulting in the exponential function in Fig. 3(a). If V_{1} is kept constant and V_{2} is swept, I_{C } can be obtained as a function of V_{CE} as shown in Fig. 3(b).
Figure 2: NPN BJT characterization circuit
(a) (b)
Figure3:Collector current(I_{C} ) of an NPN BJT as a function of (a) V_{BE } (b) V_{CE}
Characterization circuit for a PNP BJT is shown in Fig. 4. Keeping V_{2} constant and sweeping V_{1} provides I_{C } as an exponential function of V_{EB } as shown in Fig. 5(a). Sweeping V_{2} while V_{1} is kept constant provides the I_{C } vs. V_{EC }characteristics as shown in 5(b).
Figure4:PNPBJTcharacterizationcircuit
(a) (b)
Figure 5: Collector current (I_{C} ) of a PNP BJT as a function of (a) V_{EB} (b) V_{EC}
2.2 BJT DC Biasing – Resistive
Figures 6(a)and(b)show typical resistivebiasing circuits forNPNandPNPtransistors,respectively.
V_{CC}
V_{CC}
^{R}B1 ^{R}C
_{V}
_{I}_{B } ^{C}
^{R}B2
^{V}2 ^{V}RE ^{R}E
0.7
0.7
^{V}CE
_{V}_{EC}
_{I}_{B}
^{V}_{C}
R_{B2}
V_{2 } V_{RE } ^{R}_{E}
^{R}_{B1 } R_{C}
−V_{EE}
−V_{EE}
(a) (b)
Figure 6: Resistive DC biasing circuit for (a) NPN (b) PNP
For each circuit in Figs. 6(a) and (b), assume that the transistor is active, and I_{B } is negligible, which means R_{B} _{1} and
^{R}_{B} _{2} ^{form} ^{a} ^{voltage } ^{divider} ^{to} ^{set} ^{the} ^{V}_{2} ^{voltage. } ^{The}^{r}^{efo}^{r}^{e,} ^{I}_{E } ^{and} ^{I}_{C } ^{can} ^{be} ^{found} ^{as}
_{R}_{B} _{2}
_{V}_{2} _{−} _{0.7}
R
^{V}_{2} ^{≈}
B 1
+ R_{B} _{2}
^{(V}_{CC } ^{+} ^{V}_{EE} ^{) } ^{⇒ } ^{I}_{E } ^{=}
R
E
^{≈} ^{I}_{C } ^{(5)}
All assumptions must be verified to complete the DC analysis. For the circuits in Figs. 6(a) and (b), I_{B } is negligible only if I_{B} I_{RB} _{1} , which requires
_{I}_{C} _{V}_{CC} _{+} _{V}_{EE}
β R
^{I}_{B } ^{=}
^{I}_{RB} _{1} ^{≈}
B 1
+ R_{B} _{2}
(6)
ToverifythattheNPNtransistorisactive,V_{CE } ≥ V_{CE} _{,sat } should be satisfied as follows
V_{CE } = V_{CC} + V_{EE} − I_{C} (R_{C } + R_{E} ) ≥ V_{CE} _{,sat } (7) For the PNP transistor, active operation requires V_{EC } ≥ V_{EC} _{,sat } as follows
V_{EC } = V_{CC} + V_{EE} − I_{C} R_{C} + R_{E } ≥ V_{EC} _{,sat } (8)
where V_{CE} _{,sat } ≈ V_{EC} _{,sat } ≈ 0.2V
2.3 BJT DC Biasing – Current Source
An alternative method for BJT DC biasing is to use a current source connected to the emitter terminal, which directly sets the I_{E } current, and hence the I_{C } current. Figure 7(a) shows the DC biasing of an NPN BJT using a current source, which can be realized using the circuits in Fig. 7(b) or (c). Figure 8 shows the DC biasing circuit of a PNP BJT using a current source, as well as current source and current mirror realizations.
^{R}B1
^{V}CC
R_{C}
_{V}_{C}
^{I}_{B}
^{V}CC
^{I}_{x } R_{1}
^{V}CC
R_{4}
^{I}_{x}
^{R}^{B2 } ^{V}2
0.7
^{V}_{x}
^{V}_{CE}
I_{x}
R_{3 } ^{V}y R_{2}
R_{6 } R_{5}
^{−V}_{EE}
^{−V}_{EE}
^{−V}_{EE}
(a) (b) (c)
Figure 7: (a) DC biasing circuit for an NPN BJT using a current source (b) Current source (c) Current mirror
^{V}CC
^{R}^{B1 } ^{V}2 ^{V}^{x } ^{I}^{x}
^{V}CC
R_{3 } V_{y } R_{2}
^{V}CC
R_{6 } R_{5}
0.7
I_{B}
^{V}EC
V_{C}
_{I}_{x } ^{R}1
I
^{x}
_{R}_{4}
^{R}_{B2}
^{R}_{C}
^{−V}_{EE}
−V_{EE}
−V_{EE}
(a) (b) (c)
Figure 8: (a) DC biasing circuit for a PNP BJT using a current source (b) Current source (c) Current mirror
For the current sources in Figs. 7(b) and 8(b), I_{x } can be calculated as
R
_{R}_{2}
_{V}_{y} _{−} _{0.7}
^{V}_{y} ^{≈}
1
+ R_{2}
^{(V}_{CC } ^{+} ^{V}_{EE} ^{) } ^{⇒ } ^{I}_{x } ^{≈}
R
3
(9)
For the current mirrors in Figs. 7(c) and 8(c), assuming matching transistors and R_{5} = R_{6} , I_{x } can be calculated as
_{V}_{CC} _{+} _{V}_{EE} _{−} _{0.7}
^{I}_{x } ^{≈}
R_{4} + R_{5}
(10)
All transistors in Figs. 7 and 8 are assumed to be active, and all I_{B } currents are assumed to be negligible. These assumptions need to be verified after finding the DC solution.
3 Calculations
1. Design the circuits in Figs. 6(a) and 6(b) with the following specifications:
^{I}_{C} |
1mA |
^{V}_{C} |
3.5V |
^{V}_{CE} |
≥ 1V |
^{V}_{RE} |
≥ 1V |
^{V}_{CC} |
5V |
^{V}_{EE} |
0 |
β |
100 |
^{V}_{T} |
25mV |
^{I}_{supply} |
≤ 2mA |
NPN
^{I}_{C} |
1mA |
^{V}_{C} |
1.5V |
^{V}_{EC} |
≥ 1V |
^{V}_{RE} |
≥ 1V |
^{V}_{CC} |
5V |
^{V}_{EE} |
0 |
β |
100 |
^{V}_{T} |
25mV |
^{I}_{supply} |
≤ 2mA |
PNP
For both circuits, DC biasing should be insensitive to variations in β and |V_{BE} |, and I_{B } currents should be designed to be negligible.
2. Design the circuits in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the following specifications:
^{I}_{C} |
2mA |
^{V}_{C} |
3.5V |
^{V}_{CE} |
≥ 1V |
^{V}_{x} |
≥ 1.5V |
^{V}_{CC} |
5V |
^{V}_{EE} |
0 |
β |
100 |
^{V}_{T} |
25mV |
^{I}_{supply} |
≤ 5mA |
NPN
^{I}_{C} |
2mA |
^{V}_{C} |
1.5V |
^{V}_{EC} |
≥ 1V |
^{V}_{x} |
≥ 1.5V |
^{V}_{CC} |
5V |
^{V}_{EE} |
0 |
β |
100 |
^{V}_{T} |
25mV |
^{I}_{supply} |
≤ 5mA |
PNP
For both circuits, DC biasing should be insensitive to variations in β and |V_{BE} |, and I_{B } currents should be designed to be negligible.
4 Simulations
For all simulations, provide screenshots showing the schematics and the plots with the simulated values prop- erly labeled.
1. Draw the schematics for the NPN characterization circuit in Fig. 2 using the 2N3904 transistor
• Perform a DC sweep of V_{1} from 0 to 5V, while V_{2} = 5V . Export the simulation data to Excel, and plot I_{C}
^{as} ^{a} ^{function} ^{of} ^{V}_{BE} ^{.}
• Perform a DC sweep of V_{2} from 0 to 5V, while V_{1} = 2V . Export the simulation data to Excel, and plot I_{C}
^{as} ^{a} ^{function} ^{of} ^{V}_{CE} ^{.}
2. Draw the schematics for the PNP characterization circuit in Fig. 4 using the 2N3906 transistor
• Perform a DC sweep of V_{1} from -5V to 0, while V_{2} = −5V . Export the simulation data to Excel, and plot
^{I}_{C } ^{as} ^{a} ^{function} ^{of} ^{V}_{EB} ^{.}
• Perform a DC sweep of V_{2} from -5V to 0, while V_{1} = −2V . Export the simulation data to Excel, and plot
^{I}_{C } ^{as} ^{a} ^{function} ^{of} ^{V}_{EC} ^{.}
3. Draw the schematics in Figs. 6(a) and 6(b) using the calculated component values and 2N3904 and 2N3906 transistors. For both circuits, perform DC operating point or interactive simulation to obtain the DC solution for I_{C} , V_{C} , V_{RE} and V_{2} .
4. Draw the schematics in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the calculated component values and 2N3904 and 2N3906 transistors. For both circuits, perform DC operating point or interactive simulation to obtain the DC solution for I_{C} , V_{C} , V_{2} , V_{x} and V_{y} .
5 Measurements
For all measurements, provide screenshots showing the plots with the measured values properly labeled.
1. Build the NPN characterization circuit in Fig. 2 using the 2N3904 transistor
• Apply a ramp signal from 0 to 5V at 1Hz for V_{1} while V_{2} = 5V . Export the voltage measurements from the scope to Excel, and plot I_{C } as a function of V_{BE} .
• Apply a ramp signal from 0 to 5V at 1Hz for V_{2} while V_{1} = 2V . Export the voltage measurements from the scope to Excel, and plot I_{C } as a function of V_{CE} .
2. Build the PNP characterization circuit in Fig. 4 using the 2N3906 transistor
• Apply a ramp signal from -5V to 0 at 1Hz for V_{1} while V_{2 } = −5V . Export the voltage measurements from the scope to Excel, and plot I_{C } as a function of V_{EB} .
• Apply a ramp signal from -5V to 0 at 1Hz for V_{2} while V_{1 } = −2V . Export the voltage measurements from the scope to Excel, and plot I_{C } as a function of V_{EC} .
3. Build the circuits in Figs. 6(a) and 6(b) using the calculated component values and 2N3904 and 2N3906 tran- sistors. For both circuits, measure the DC values for I_{C} , V_{C} , V_{RE} and V_{2} using the voltmeter or scope.
4. Build the circuits in Figs. 7(a) and 8(a) using the current sources in Figs. 7(b) and 8(b), respectively, with the calculated component values and 2N3904 and 2N3906 transistors. For both circuits, measure the DC values for I_{C} , V_{C} , V_{2} , V_{x} and V_{y} using the voltmeter or scope.
6 Report
1. Include calculations, schematics, simulation plots, and measurement plots.
2. Prepare a table showing calculated, simulated and measured results.
3. Compare the results and comment on the differences.
7 Demonstration
1. Build the circuits in Figs. 2, 4, 6(a), 6(b), 7(a)&(b) and 8(a)&(b) on your breadboard and bring it to your lab session.
2. Your name and UIN must be written on the side of your breadboard.
3. Submit your report to your TA at the beginning of your lab session.
4. For the NPN characterization circuit in Fig. 2:
• Apply a ramp 0 to 5V at 1Hz for V_{1} while V_{2} = 5V , and export the measurements from scope to Excel.
• Plot I_{C } as a function of V_{BE } in Excel.
5. For the PNP characterization circuit in Fig. 4:
• Apply a ramp -5V to 0 at 1Hz for V_{2} while V_{1} = −2V , and export the measurements from scope to Excel.
• Plot I_{C } as a function of V_{EC} in Excel.
6. For the resistive NPN and PNP biasing circuits in Figs. 6(a) and 6(b):
• Measure the DC voltages V_{C} , V_{B} , V_{E} .
• Calculate I_{C } from the voltage measurements.
7. For the current-source NPN and PNP biasing circuits in Figs. 7(a)&(b) and 8(a)&(b):
• Measure the DC voltages V_{C} , V_{B} , V_{E} for both transistors.
• Calculate I_{C } from the voltage measurements.