$30.00
Description
Assume for the rest of this problem that all logic gates have the following delays:

Fan In
Delay
1
T
2
2T
3
3T
4
5T
5
7T
6
10T
7 or more
2T x fanin
So a 2input AND gate would have delay 2T and a 4input OR gate would have delay 5T.
For simplicity, assume that mux’s have delay 4T regardless of fanin.
We will create a 32bit adder out of some building blocks we’ve covered in class. We will use the 4bit CLA that we covered in class as one basic building block of this design. And we will use it (as we did in class) to make 16bit hierarchical CLAs (HCLA) which will be our other building block. But instead of connecting these in series to make a 32bit adder, we will use carry select to speed up the 32bit adder. The design will look as follows (be sure to note where we are using CLAs and where we are using HCLAs):
Your task is to find the maximal delay of this design – i.e. determine the delays of S031 and C32 – the maximal delay of these outputs will be the maximal delay of the design. Fill in the values in the table on the following page to receive full credit (and to help with possible partial credit).

Output
Delay
(2 points)
G0
P0
(2 points)
Gα
(2 points)
Pα
(2 points)
C12
(2 points)
C15
(2 points)
C16
(2 points)
S15
(2 points)
C20
(2 points)
S19
(2 points)
C24
(2 points)
C31
(2 points)
C32 (after mux)
(2 points)
S31 (after mux)
(2 points)
Find the maximum delay in terms of T of the 32bit adder – take the maximum of all output bits – including the sum bits (S0S31) and the final carry out (C32). Show your work clearly in the table above. The two figures on the following pages are taken from the class notes, if you need to refer to them.
Maximal Delay: _______________ (2 points)