Assume for the rest of this problem that all logic gates have the following delays:
7 or more
2T x fan-in
So a 2-input AND gate would have delay 2T and a 4-input OR gate would have delay 5T.
For simplicity, assume that mux’s have delay 4T regardless of fan-in.
We will create a 32-bit adder out of some building blocks we’ve covered in class. We will use the 4-bit CLA that we covered in class as one basic building block of this design. And we will use it (as we did in class) to make 16-bit hierarchical CLAs (HCLA) which will be our other building block. But instead of connecting these in series to make a 32-bit adder, we will use carry select to speed up the 32-bit adder. The design will look as follows (be sure to note where we are using CLAs and where we are using HCLAs):
Your task is to find the maximal delay of this design – i.e. determine the delays of S0-31 and C32 – the maximal delay of these outputs will be the maximal delay of the design. Fill in the values in the table on the following page to receive full credit (and to help with possible partial credit).
C32 (after mux)
S31 (after mux)
Find the maximum delay in terms of T of the 32-bit adder – take the maximum of all output bits – including the sum bits (S0-S31) and the final carry out (C32). Show your work clearly in the table above. The two figures on the following pages are taken from the class notes, if you need to refer to them.
Maximal Delay: _______________ (2 points)