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Objective: In this experiment, you will use Logisim to analyse and design sequential circuits. Part I Run Logisim, open the file lab10part1.circ. The circuit is shown below. The circuit consists of two JK flip-flop and an OR gate. Note the following: The outputs of the two JK flip-flops are labelled A…
Objective:
In this experiment, you will use Logisim to analyse and design sequential circuits.
Part I
AY2019/20 Semester 2 – 1 of 3 – CS2100 Lab #10
For flip-flop A: | JA=A+B; | KA=0 | ||||||||||
For flip-flop B: | JB=1; | KB=A+B | ||||||||||
3. Complete the following table: | [6 marks] | |||||||||||
Present state | Flip-flop inputs | Next state | ||||||||||
A | B | JA | KA | JB | KB | A+ | B+ | |||||
0 | 0 | |||||||||||
0 | 1 | |||||||||||
1 | 0 | |||||||||||
1 | 1 | |||||||||||
00
01 10
11
AY2019/20 Semester 2 – 2 of 3 – CS2100 Lab #10
Part II
For flip-flop A: | JA=1; | KA=A B | |||||||||
For flip-flop B: | JB=0; | KB = (A B)’ | |||||||||
7. Complete the following table: | [6 marks] | ||||||||||
Present state | Flip-flop inputs | Next state | |||||||||
A | B | JA | KA | JB | KB | A+ | B+ | ||||
0 | 0 | ||||||||||
0 | 1 | ||||||||||
1 | 0 | ||||||||||
1 | 1 | ||||||||||
8. Complete the state diagram below. | [4 marks] |
00 | |
01 | 10 |
11 |
input so that you can set both flip-flops to 1. [5 marks]
Total: 25 marks
AY2019/20 Semester 2 – 3 of 3 – CS2100 Lab #10