Solved–Verilog Programming– Lab 2:– Solution

Description

Objectives:
1. Interfacing simple input output devices connected to an FPGA chip, such as LEDs and switches
2. Download and test the design on Altera DE0-CV board
3. Create digital circuit by using Verilog code
4. Design a circuit that can drives 7-segment displays

In-lab demonstration:
1. Light up a LED by using a switch (Schematic Design) – 10 points
2. Light up a LED if more than two switches are 1 (Verilog Design) – 15 points

3. Correctly show the hex values on 7-segment Displays – 25 points

What to hand in:
1. TA checkoff sheet with TA’s grading and signature.

1. Introduction to DE0-CV Board

The DE0-CV board provides 10 slide switches (called SW[0], SW[1], …, SW[9]), 4 user-defined push-buttons (KEY[3], …, KEY[0]), and 10 user-controllable red LEDs (called LEDR[0], LEDR[1], …, LEDR[9]). The switches and push buttons can be used to provide inputs, and the lights can be used as output devices.

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

• LEDs (light-emitting diodes) are digital lights. Each LED is controlled by a single wire.

• A slide switch is used to input a value (0 or 1) to the FPGA chip. These switches are not debounced. When a switch is in the DOWN position (closest to the edge of the board), it provides a low logic level to the FPGA, and when a switch is in the UP position it provides a high logic level.

• Each push-button switch provides a high logic level when it is not pressed, and provides a low logic level when depressed. The push-button are debounced by hardware.

The DE0-CV board has hardwired connections between the pins of the FPGA chip and on-board devices (such as switches and LEDs).

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

2. Light up a LED by using a Switch (Schematic Design)

In this project, you will develop a project that uses a slide switch to light up a LED by using the schematic design. Follow the following steps:

1) Create a new project

a. File → New Project Wizard
b. Named the project as LED_Schematic

c. Select the device 5CEBA4F23C7 in the Cyclone V family, which is the FPGA chip on the Altera DE2 board.

You can also change the device: Assignments → Device → Select Cyclone V 5CEBA4F23C7 as the target chip

2) Create a Schematic Design, and make it as the top entity. The Schematic Design will have one input pin and one output pin. The input pin is named as SW[0] and the output pin is named as LEDR[0]. The two PINs are connected via a NOT gate.

3) Assign Pins to connect switches/lights to inputs and outputs of your circuit. Click Assignments, then Import Assignments…, import the pin assignment file “DE0_CV.qsf”. After importing the PIN assignment file, you can use pre-defined pin names, instead of pin numbers, to directly access input or output pins.

Signal Name FPGA Pin No. Description
KEY0 PIN_U7 Push button 0
… … …
KEY3 PIN_M6 Push button 3
SW0 PIN_U13 Slide switch 0
… … …
SW9 PIN_AB12 Slide switch 9
LEDR0 PIN_AA2 LED 0
… … …
LEDR9 PIN_L1 LED 9

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

4) Synthesis/Compile: The compile process may take over twenty minutes. A smart compiler

can significantly reduce the compile time. Follow the menu: “Processing” → “Compiler Tool” → “Analysis & Synthesis Settings”. If your project is large (such as Projects of this course), enabling smart compilation will significantly save you compilation time.

5) Downloading the LED_Schematic.sof file to the DE0-CV board through USB-Blaster.

a) Connect the DE0-CV board to the host computer by means of a USB cable plugged into the USB-Blaster port.

b) Turn on the power to the DE0-CV board. Ensure that the RUN/PROG switch is in the RUN position.
c) Select Tools → Programmer.

d) If not already chosen by default, select JTAG in the Mode box. Also, if the USB-Blaster is not chosen by default, click the “Hardware Setup…” button and select the USB-Blaster in the window that pops up. Note: if USB-Blaster does not appear, go to “Devices” in Windows and check the box that says “Altera USB-Blaster”

e) If you use your own computer to program the Altera DE0-CV boards, you might need to install the USB-Blaster Driver. You can download the driver from here: http://www.altera.com/download/drivers/dri-index.html

f) The configuration file yourproject.sof should be listed in the window. If the file is not already listed, then click
g) Add file and select it.
h) Click the box under Program/Configure to select this action.
i) Press Start to configure the FPGA.

6) Demo to TA if you complete.

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

3. Light up a LED by using Switches (Verilog Coding)

In this section, we will repeat the task in Verilog.

1) Create a new project

a. File → New Project Wizard (Make sure that this project is stored in a different folder than your previous one)

b. Named the project as LED_Verilog
c. Select the device 5CEBA4F23C7 (DE0-CV) in the Cyclone V family

2) Perform PIN assignment as Step 2 of the previous project.

3) Crate a Verilog File invoked through Quartus’ File menu (File → New → Device Design Files tab
→ Verilog HDL File)

4) Type in the following Verilog code and save the code as top.v

a. Save the code as top.v (File → Save As). Quartus adds the “.v” extension automatically, so you need only type top as the file name.
b. Make sure the box is checked to add this file automatically to the current project.

5) Demo to TA after you complete.

/ file top.v
/ The output of the LED will be 1 if and only if
/ two or more of the dip switches are 1.

module top(

input wire [9:0] SW,
output reg [9:0] LEDR);

always @* begin
if (SW[0] == 1’b1 && SW[1] == 1’b1) begin
LEDR[0] = 1’b1;

end else if (SW[0] == 1’b1 && SW[2] == 1’b1) begin LEDR[0] = 1’b1;

end else if (SW[1] == 1’b1 && SW[2] == 1’b1) begin LEDR[0] = 1’b1;

end else begin
LEDR[0] = 1’b0; // default value is 0
end
end

endmodule

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

A few points about the Verilog code above:

a. The code describes the circuit for the module top. This module name corresponds to the name of the top-level design entity you specified when creating the Quartus project.

b. 1’b0 and 1’b1 are how you express numbers in Verilog. The number before the ‘ indicates the number of bits in the number; in this case, we are expressing a 1-bit number. The letter after the ‘ indicates which base the number is in; in this case, we are expressing numbers in base 2, or binary, denoted by the letter b. The number after the letter indicates the value of the number; in this case, we are expressing the numbers 0 and 1. Other possible bases for expressing numbers are decimal (denoted by the letter d) and hexadecimal (denoted by the letter h). For example, an 8-bit number with the value 200 could be written as 8’d200 or 8’b11001000 or 8’hc8.

c. The module takes an input variable (SW) and produces an output variable (LEDR). Each variable is declared as an array of 10 bits (bits 9 through 0). The file top.qsf that you downloaded when you created the project connects the SW array to the 18 dip switches on the DE0-CV. Similarly, top.qsf connects the LEDR array to the 18 red LEDs on the DE0-CV.

d. Each variable in Verilog (such as SW and LEDR) is declared as type wire or type reg. Use the following rule to determine which type to use for a variable: if the variable is assigned a value in the module (through a statement such as LEDR[0] = 1’b1), it should be declared reg. Otherwise it should be declared wire.

e. The code block starting with always @* specifies the relationship between LEDR and SW. It specifies how the value of LEDR[0] (the 0th element of the LEDR array) depends on the values of SW[0], SW[1], and SW[2]. always @* means “continuously drive the wire LEDR based on the value of computed in this block. In this case, the value will depend on SW and will implement a “majority vote”: the output of the LED will be 1 if and only if two or more of the dip switches are 1.

f. The syntax of Verilog is like that of C++.

a. The operators = , ==, and && have the same meaning as in C++. Other operators that have the same meaning as in C++ are comparison operators (<, >, <=, >=, !=), logical operators (&&, ||, !), addition/subtraction (+, -), and bitwise operators (<<, >>, &, |, ~). (Avoid using from multiply/divide (*, /), as they are difficult to synthesize into an FPGA circuit.)

b. If … else if … else work exactly as they do in C++. All if statements in Verilog should end with an unconditional else clause.

c. begin … end are used to group lines of code into a single block, just as { … } work in C++.

d. As with C++, Verilog ignores white space, uses // or /* … */ for comments, and is case sensitive.

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Lab 2 EECE473 Computer Organization & Architecture University of Maine

4. Seven-segment LEDs based on Multi-module Verilog

The DE0-CV board has six 7-segment displays (HEX0, …, HEX5). Each segment in a display is indexed from 0 to 6, with corresponding positions given in the following figure.

Create a new Quartus project called SevenSegmentLED. As always, the top-level design entity for the project will be a module named top.

Next, complete the Verilog module hexdecoder. It takes as input a 4-bit number (in) and produces a 7-bit array of values (out) based on the input value. The bits of out are meant to control the segments of a 7-segment LED, as per the following diagram:

out[0]
——–
| |
out[5] | | out[1]
| out[6] |
——–
| |
out[4] | | out[2]
| |
——–
out[3]

For each bit of out, the value 0 causes that segment of the LED to be lit, and the value 1 causes that segment of the LED to be off. This is opposite from the LEDR devices you used in Lab 1. Complete the code so that the value of out returned by hexdecoder generates a human-readable picture of the input value on the 7-segment LED.

Remember that each output value must be defined for each combination of input values (usually by having an unconditional else clause in each if statement). Also remember that multi-bit values are specified with the most-significant bit on the left. E.g., out = 7’b0110000; is shorthand for:

out[6] = 1’b0;
out[5] = 1’b1;
out[4] = 1’b1;
out[3] = 1’b0;
out[2] = 1’b0;
out[1] = 1’b0;

out[0] = 1’b0;

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Lab 2 EECE473 Computer Organization & Architecture University of Maine
The table below shows the pin names of the 7-segment displays.

Display Wires for Wires for Wires for Wires for Wires for Wires for
Segment HEX0 HEX1 HEX2 HEX3 HEX4 HEX5

0 HEX0[0] HEX1[0] HEX2[0] HEX3[0] HEX4[0] HEX5[0]
1 HEX0[1] HEX1[1] HEX2[1] HEX3[1] HEX4[1] HEX5[1]
2 HEX0[2] HEX1[2] HEX2[2] HEX3[2] HEX4[2] HEX5[2]
3 HEX0[3] HEX1[3] HEX2[3] HEX3[3] HEX4[3] HEX5[3]
4 HEX0[4] HEX1[4] HEX2[4] HEX3[4] HEX4[4] HEX5[4]
5 HEX0[5] HEX1[5] HEX2[5] HEX3[5] HEX4[5] HEX5[5]
6 HEX0[6] HEX1[6] HEX2[6] HEX3[6] HEX4[6] HEX5[6]

We wish to display on the 7-segment displays HEX1 and HEX0 the values set by the switches SW7 to SW0. The following is the top.v. We can toggle the slide switches to change the values shown on the 7-segment displays.

// file top.v
module top( SW, HEX0, HEX1 );

input wire [7:0] SW; output wire [6:0] HEX0; output wire [6:0] HEX1;

/ slide switches
/ 7-seg display 0
/ 7-seg display 1

hexdecoder (SW[3:0], HEX0); // display value denoted by switches 3-0 hexdecoder (SW[7:4], HEX1); // display value denoted by switches 7-4

endmodule

The following is an incomplete hexdecoder.v and please complete the code.

// file hexdecoder.v

module hexdecoder ( in, out );

input wire [3:0] in;
output reg [6:0] out;

always @* begin
if (in == 4’h0) begin
out =

end

endmodule

Compile, download, and test your circuit. You should use the switches to control the value of 7-segment LEDs display. Demo to TA if you complete.

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Lab 2 EECE473 Computer Organization & Architecture University of Maine
ECE 473 Lab 2
TA Checkoff Sheet
Name: ____________________________
Date: _____________________________
Final Grade: ________________________

1) Light up a LED by using a switch (Schematic Design) – 10 points

Grade_______________________

TA Signature: _____________________________, Time: _________________________

Comments:

2) Light up a LED if more than two switches are 1 (Verilog Design) – 15 points Grade_______________________

TA Signature: _____________________________, Time: _________________________

Comments:

3) Correctly show the hex values on 7-segment displays – 25 points

Grade_______________________

TA Signature: _____________________________, Time: _________________________

Comments:

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