Solved–Lab 3– Solution

Description

1. Preparation

1. 1. Read this document in its entirety.

1. 2. Draw a circuit showing how you might build a 4⇥1 mux from 2⇥1 muxes.

1. 3. Read Example 2.23 in the main textbook on pages 72–73 and prepare the truth table for a 4-bit binary number to hexadecimal 7-segment display. That is, in addition to 0-9, the display also shows A, b, C, d, E, and F.

1. 4. Read the 2-page reference manual (attached to the end of this document) to better understand the seven-segment display connections.

2. Multiplexer Design

2.1 Building a 4⇥1 Mux

Inside your ECE2700 directory, create a new folder called Lab3. Start up Xilinx and create a new project called MuxExp inside the Lab3 directory.

Create a new file called mux4x1.v. Inside, design a 4⇥1 mux using the provided 2⇥1 mux (mux2x1.v on Canvas).

Be sure to declare your 4⇥1 mux as follows: module mux4x1(I3, I2, I1, I0, S1, S0, D), where I3, I2, I1, and I0 are data inputs, S1 and S0 are control inputs, and D is the output. Make sure to design your mux such that when S0 = 0, S1 = 0, D = I0, and when S0 = 1, S1 = 1, D = I3.

Test your design using the bench file mux4test.v from Canvas. Show your results to the TA.

2.2 Using the Muxes

Create a new file called shifter.v. You are to design a simple shifter using the 4⇥1 mux(es) you designed in earlier. The shifter has four 1-bit data inputs (i3, i2, i1, i0), two 1-bit control inputs (s1, s0), and four 1-bit data outputs (d3, d2, d1, d0). The following table describes the desired behaviors of the shifter. Be sure to declare your shifter as follows: module shifter(i3, i2, i1, i0, s1, s0, d3, d2, d1, d0). Observe that i3 is the leftmost bit in the input.

Hint: Remember that a mux is simply a circuit that selects the output from one of the inputs. Think about what the data and control inputs need to be for the shifter to work correctly.

Test your design using the bench file testshifter.v from Canvas. Show your results to the TA.

3 Decoder Design

3.1 Simple 7-Segment Display

For this part of the lab you will write code for the 7-segment display and load it onto the Basys board. Create a new project called SevenSeg. Add a new source file seg7.v and write out your binary number to hexadecimal 7-segment display using the following declaration: seg7(w, x, y, z, a, b, c, d, e, f , g), where w, x, y, and z are the 4-bit binary input and a, b, c, d, e, f , and g are the outputs. (If you are unsure what to do, remember that you have prepared a truth table. From the truth table, you can convert to Boolean equations and write them directly in Verilog.) Run simulations to make sure your design is correct.

Locate SW0, SW1, SW2, and SW3 on the Basys board. These switches will represent the 4-bit binary number input. As mentioned earlier, the output (corresponding hex value) will be displayed on the 7-segment display. From reading the reference manual and looking inside MainBasys.ucf, you will see that although the 7-segment display contains 4 digits, there are only 7 pin assignments for the 7-segment LEDs, not 28.

NET “seg<0>” LOC = “p25”; # Bank = 3, Signal name = CA

NET “seg<1>” LOC = “p16”; # Bank = 3, Signal name = CB

NET “seg<2>” LOC = “p23”; # Bank = 3, Signal name = CC

NET “seg<3>” LOC = “p21”; # Bank = 3, Signal name = CD

NET “seg<4>” LOC = “p20”; # Bank = 3, Signal name = CE

NET “seg<5>” LOC = “p17”; # Bank = 3, Signal name = CF

NET “seg<6>” LOC = “p83”; # Bank = 1, Signal name = CG

This is to reduce the number of pins on the board. You can determine which of the 4 digits (or all of them) are displayed by sending appropriate signals to the following anodes.

NET “an<3>” LOC = “p26”; # Bank = 3, Signal name = AN3

NET “an<2>” LOC = “p32”; # Bank = 3, Signal name = AN2

NET “an<1>” LOC = “p33”; # Bank = 3, Signal name = AN1

NET “an<0>” LOC = “p34”; # Bank = 3, Signal name = AN0

Be Careful! The inputs for the 7-segment LEDs and the anodes are active low. In other words, to display an 8 on the rightmost digit, you will set a, b, c, d, e, f , and g all to 0. In addition, you will set the input corresponding to an<0> to 0 and set all the other inputs to the anodes to 1.

Add a new file called SevenSeg.v with the following declaration: SevenSeg(w, x, y, z, a, b, c, d, e, f , g, n3, n2, n1, n0). Here, n0 corresponds to the signal sent to anode 0 (AN0). Write necessary code so that only the rightmost digit lights up. Recall that you will need to add a .ucf file to indicate pin assignments. Generate the corresponding bit file, test your design and show the results to the TA.

4. TA Checko↵

4. • (20 points) Pre-lab.

4. • (40 points) 4⇥1 mux design.

4. • (60 points) Shifter design.

4. • (80 points) 7-segment display.

PmodSSD Reference Manual Digilent, Inc.

www.digilentinc.com Copyright Digilent, Inc. Page 2