Solved-Lab 4 Latches, Flip- ops, and Registers -Solution

Description

• Learning Objectives

The purpose of this lab is to investigate the fundamental synchronous logic elements: latches, ip- ops, and registers. In this lab you will build a gated D-Latch with the 7400 logic chips and write Verilog to create a registered ALU and a shift register.

• Marking Scheme

Each lab is worth 4% of your nal grade, but you will be graded out of 8 marks for this lab, as follows.

• Prelab + Simulations: 3 marks

• Part I (in-lab): 1 mark

• Part II (in-lab): 2 mark

• Part III (in-lab): 2 marks

• Preparation Before the Lab

You are required to complete the prelab for Part I of the lab as you would have prepared for Lab 1. Parts

35. and III of the lab require you to write and test your Verilog code. Include your schematics, Verilog, and simulations (where applicable) for Parts I to III in the prelab. You must simulate your circuits with ModelSim (using reasonable test vectors using ModelSim scripts).

In-lab Work

You are required to implement and test all of Parts I to III of the lab. You need to demonstrate all parts to TAs after you tested them yourselves.

• Latches in Verilog

In modern digital circuit design, latches are rarely used, and only in very special circumstances. On FPGAs especially, we seldom use latches except in very speci c designs. Most of the time, if we create a latch in Verilog in a design for an FPGA, we have created the latch in error. To explore the behaviour of latches, in this lab you will create a latch using only the 7400 logic chips.

In Verilog, when we use always @(*) to create combinational logic, we sometimes inadvertently create latches. For instance, this happens when you use the equal (=) sign to set an output value, but don’t specify what the output should be for all possible combinations of input values. The circuit assumes it has to retain a past value in those cases, creating a latch.

For example in the following code:

reg w;

always @( ∗ )

begin

i f ( x ) // when x i s t r u e ( i . e . , l o g i c 1)

w = 1 ; // w g e t s s e t t o 1

end

w does not have a value speci ed when x is 0. In this instance a latch would be created. To x this code and create a proper combinational circuit, w should have a value speci ed for all possible values of inputs, meaning that the truth table for the logic function is fully speci ed. From now on, you should check your compilation log in Quartus and look out for warnings that latches have been created. An example warning message may look like this:

Warning (10240): Verilog HDL Always Construct warning at mymodule.v(9): inferring latch(es) for variable \w”, which holds its previous value in one or more paths through the always construct

The warning message clearly identi es that identi er w caused the latch to be created. It also points to the le (mymodule.v) and line number (9) where the o ending always block resides. In your code, the module name, identi er name, and line number will be di erent, of course. Note that this is a warning message (as opposed to an error or critical warning), so make sure that your lters in the Messages window are not set to hide warning messages. Message ltering can be achieved by clicking on the red circle (for error messages), yellow triangle (for warnings), and purple triangle (for critical warnings). The Messages window is usually situated at the bottom of the Quartus window. If you closed this window by mistake, you can enable it again by selecting View > Utility Windows > Messages.

• Shift Operators in Verilog

Verilog has the following two logic shift operators: (a) Logic Right Shift operator (>>) and (b) Logic Left Shift operator (<<). Doing (A >> N) shifts A by N bits to the right; the N most signi cant bits of the resulting vector are lled-in with zeros. Doing (A << N) shifts A by N bits to the left; the N least signi cant bits of the resulting vector are lled-in with zeros. As with any combinational circuit A and N are inputs to the circuit and the shifted result is the output.

Here is a Verilog snippet that uses these two operators:

wire [ 2 : 0 ] a , b ;

wire c ;

assign c = 1 ’ b1 ;

assign a = ( 3 ’ b011 >> 1 ’ b1 ) ; // a i s 3 ’ b011 s h i f t e d r i g h t one b i t

// r e s u l t : a = 3 ’ b001

assign b = a << c ; // b i s a s h i f t e d l e f t one b i t

// r e s u l t : b = 3 ’ b010

• Part I

Figure 1 shows the circuit for a gated D latch. In this part, you will build the gated D latch using the 7400 chips (as in Lab 1) on the protoboard (breadboard). Refer back to the Lab 1 handout for 7400 chips schematics, speci cations, and pin-out.

Figure 1: Circuit for a gated D latch.

Perform the following steps:

1. In your pre-lab, draw a schematic of the gated D latch using interconnected 7400-series chips. For this exercise you are allowed to use NAND gates. Recall from Lab 1 what a gate-level schematic looks like. (PRELAB)

2. Build the gated D latch using the chips on the protoboard. Use switches to control the clock (Clk) and D input. Use lights (LEDs) to make Qa and Qb visible. Don’t forget to hook up the power and ground on all of your chips!

3. Study the behaviour of the latch for di erent D and clock (Clk) settings.

4. Are there any input combinations of Clk and D that should NOT be the rst you test? Explain this in your prelab and list them if applicable. (PRELAB)

5. Demonstrate your latch implementation to the TA after you have tested it. (IN-LAB)

• Part II

The most common storage element today is the edge-triggered D ip- op. One way to build an edge-triggered D ip- op is to connect two D latches in series, such that the two D latches use opposite levels of the clock for gating the latch. This is called a master-slave ip- op. The output of the master-slave ip- op changes on a clock edge, unlike the latch, which changes according to the level of the clock. For a positive edge-triggered ip- op, the output changes when the clock edge rises, i.e., when clock transitions from 0 to 1. The Verilog code for a positive edge-triggered ip- op is shown in Figure 2. This ip- op also has an active-low, synchronous reset, meaning that the reset only happens when reset n is 0 on the rising clock edge. If q is declared as reg q, then you get a single ip- op. If q is declared as reg[7:0] q, then you get eight parallel ip- ops, which is called an 8-bit register. Of course, d should have the same width as q.

• For a negative edge-triggered ip- op, substitute the posedge keyword with negedge.

always @( posedge c l o c k )

//

T r i g g e r e d

e v e r y

time c l o c k r i s e s

//

Note

t h a t

c l o c k

i s

not

a

keyword

begin

i f ( r e s e t n == 1 ’ b0 )

//

When

r e s e t

n

i s

0

//

Note

t h i s

i s

t e s t e d

on

e v e r y

r i s i n g c l o c k

e d g e

q <= 0 ;

// S e t q t o 0 .

//

Note

t h a t

t h e

a s s i g n m e n t

u s e s

<= i n s t e a d

o f =

e l s e

//

When

r e s e t

n

i s

not

0

q <= d ;

// S t o r e t h e v a l u e o f d i n q

end

Figure 2: Verilog for a positive edge-triggered ip- op with active-low, synchronous reset¹.

Note that all assignment statements in the aforementioned code use <= instead of =. From now on you should use the assignment operator = only for combinational circuits, and the assignment opera-tor <= for sequential circuits. Sequential circuits are circuits where the output relies not just on the current combination of inputs, but also on the prior state of the circuit (i.e., its prior input sequence). Combinational circuits are described using assign statements or always @(*) blocks, while sequential circuits are described using always @(posedge…) and always @(negedge…) blocks. Note that you can place multiple statements inside of an if-else statement if you enclose such statements inside of a begin-end block.

Starting with the circuit you built for Lab 3 Part III, build an ALU that supports the eight operations shown in the pseudo-code in Figure 3. The output of the ALU is to be stored in an 8-bit register and the four least-signi cant bits of the register output are to be connected to the B input of the ALU. Figure 4 shows the required connections.

always @( ∗ )

// D e c l a r e

a l w a y s

b l o c k

begin

case ( ALU function ) // S t a r t

o f t h e c a s e s t a t e m e n t

0: …

//

Make t h e

o u t p u t

e q u a l

t o A+1, u s i n g

t h e

adder

//

c i r c u i t

from Part I I

o f

Lab

3 .

1: …

//

A + B

u s i n g

t h e

adder

from

Part

I I

o f Lab

3

2: …

// A + B u s i n g t h e V e r i l o g ‘ +’ o p e r a t o r

3: …

//

AXORB

i n

t h e l o w e r

f o u r

b i t s ,

AORB

i n

t h e upper f o u r b i t s

4: …

//

Output

1

( 8 ’ b00000001 )

i f

any o f t h e 8

b i t s

i n

//

e i t h e r

A

or

B a r e h i g h ,

and

0

( 8 ’ b00000000 )

//

i f a l l

t h e

b i t s

a r e low ( use a

r e d u c t i o n OR

o p e r a t o r )

5: …

// L e f t s h i f t B by A b i t s

6: …

// R i g h t s h i f t B by A b i t s ( l o g i c a l r i g h t s h i f t )

7: …

// A B u s i n g t h e V e r i l o g ∗ o p e r a t o r

default : . . .

//

D e f a u l t

c a s e ( i f

needed )

endcase

end

Figure 3: Pseudo-code for ALU.

Perform the following steps.

1. Create a Verilog module for the simple ALU with register, with the following speci cations: (PRELAB)

1. • Use the code in Figure 2 as the model for your register code.

1. • Connect the Data (A) input of your ALU to switches SW_{3 0}.

Data
HEX Display
4	Signal A	4	Signal B
		ALU
		8
		Register
		8

HEX Display

LED Display

Figure 4: Simple ALU with register circuit for Part II.

1. • Connect KEY₀ to the Clock input for the register, SW₉ to reset n and use SW_{7 5} for the ALU function inputs.

1. • Display the ALU outputs on LEDR_{7 0}; have HEX0 display the value of Data (A) in hexadec-imal and set HEX1, HEX2 and HEX3 to display nothing (all segments o ).

1. • HEX4 and HEX5 should display the least-signi cant and most-signi cant four bits of Register (ALU outputs) respectively, also in hexadecimal.

2. Simulate your circuit with ModelSim, ensuring the output waveforms are correct for each of your test cases. Choose test cases that make you feel con dent about your ALU’s correctness, in prepa-ration for you in-lab demo. Your prelab should include at least one test for each ALU operation, though more test cases per operation is advisable. Make sure to include a few selected screenshots of these cases when you hand in your prelab. (PRELAB)

3. Create a new Quartus Prime project for your circuit. Make sure it is stored in your W:\ drive. Do not forget to select the correct FPGA device (5CSEMA5F31C6) and import the pin assignments.

4. Compile the project.

5. Download the compiled circuit into the FPGA chip and test the functionality of the circuit. When it is working as it should, show it to TAs. (IN-LAB)

• Part III

In this part of the lab, you will create an 8-bit shift-register that has an optional arithmetic shift. A shift register is a collection of ip- ops that move values sequentially between each other on each clock edge. Figure 5 shows one bit of this shift-register. It contains a positive edge-triggered ip- op and two multiplexers. To create an 8-bits shift-register, you will use eight instances of the circuit in Figure 5 to design your 8-bit shift-register with optional arithmetic shift and parallel load as shown in Figure 6.

ShifterBit
load_val
	0	0	D	Q	out
in		1
	1
	shift	load n	clk	reset_n
				reset_n

Figure 5: Single-bit shift-register

Shifter

8. ^LoadVal

Load_n	ShifterBit			ShifterBit			ShifterBit
ShiftRight
ASR			…
clk
reset_n

Q[7]

Q[1]

Q[0]

Figure 6: 8-bit shift-register of Part III. None of internal connections are shown here.

When bits are shifted in this register, it means that the bits are copied to the next ip- op on the right. For example, to shift the bits right, each ip- op loads the value of the ip- op to its left when the clock edge occurs. In the right-shift, the ip- op at the left end of the register has no left neighbour. One option is to load a zero, but what if the value in the register is signed? In this case we should perform sign-extension. When we perform the sign-extension, this shift operation is called an Arithmetic Shift Right (ASR).

In the Shifter module, create an 8-bit-wide register input LoadVal, whose individual wires are connected to load val input of ShifterBit instances. Likewise, create an 8-bit-wide output Q, which is the output of ShifterBit instances. The shift input of all eight instances of the circuit in Figure 5 should be connected to the single input ShiftRight. The same thing applies to load n, clock (clk), and reset n.

The in input of seven instances should be connected to the out port of the instance to its left. For the leftmost ShifterBit, you should design a circuit that will perform sign-extension when the signal ASR is high (arithmetic right shift) or load zeros if ASR is low (logic right shift). This special circuit is not shown in Figure 6.

Here is an example of the circuit operation:

1. When Load n = 0, the value on LoadVal is stored in the ip- ops on the next positive clock edge (i.e., parallel load behaviour).

2. When Load n = 1, ShiftRight = 1 and ASR = 0, the bits of the register shift to the right on each positive clock edge. Assuming that the initial value in the ip- ops at cycle 0 is A, with bits A₇ through A₀, the values in the two subsequent cycles would be:

	Q[7]	Q[6]	Q[5]	Q[4]	Q[3]	Q[2]	Q[1]	Q[0]
Cycle 0:	A7	A6	A5	A4	A3	A2	A1	A0
Cycle 1:	0	A7	A6	A5	A4	A3	A2	A1
Cycle 2:	0	0	A7	A6	A5	A4	A3	A2
				: : :

3. When Load n = 1, ShiftRight = 1 and ASR = 1 the bits of the register shift to the right on each positive clock edge but the most signi cant bit is replicated. This is called an Arithmetic shift right:

		Q[7]	Q[6]	Q[5]	Q[4]	Q[3]	Q[2]	Q[1]	Q[0]
	Cycle 0:	A7	A6	A5	A4	A3	A2	A1	A0
	Cycle 1:	A7	A7	A6	A5	A4	A3	A2	A1
	Cycle 2:	A7	A7	A7	A6	A5	A4	A3	A2
					: : :
Do the following steps:

1. What is the behaviour of the 8-bit shift register shown in Figure 6 when Load n = 1 and ShiftRight = 0 ? Brie y explain in your prelab. (PRELAB)

2. Draw a schematic for the 8-bit shift register shown in Figure 6 including the necessary connections. Your schematic should contain eight instances of the one-bit shifter shown in Figure 5 and all the wiring required to implement the desired behaviour. Label the signals on your schematic with the same names you will use in your Verilog code. (PRELAB)

3. Starting with the code in Figure 2 for a positive edge-triggered D ip- op, use this D ip- op with instances of the mux2to1 module from Lab 2 to build the one-bit shifter shown in Figure 5. To get you started, Figure 7 is a code snippet that shows how the D ip- op will be connected to one of the 2-to-1 multiplexers. (PRELAB)

Use KEY₁ as the Load n input, KEY₂ as the ShiftRight input and KEY₃ as the ASR input. Use KEY₀ as the clock (clk). The outputs Q_{7 0} should be displayed on LEDR_{7 0}. (PRELAB)

5. Compile your Verilog code and simulate the design with ModelSim. In your simulation, you should perform the reset operation on the rst clock cycle, then do a parallel load of your register on the next cycle. Finally, clock the register for several cycles to demonstrate both types of shifts. (NOTE: If you do not perform a reset rst, your simulation will not work! Try simulating without doing reset rst and see what happens. Can you explain the results?) Include one (or a few) screenshot of simulation output in your prelab. (PRELAB)

5. Create a new Quartus Prime project for your circuit. Make sure it is stored in your W:\ drive. And do not forget to select the correct FPGA device (5CSEMA5F31C6), as well as importing the pin assignments.

5. Compile the project and download your circuit on the DE1-SoC board. Then test the functionality of your shift register and show it to your TAs when you nished testing. (IN-LAB)

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