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Objectives: In this experiment, you will design, connect and test a 3-bit Majority Logic Circuit. The design of this circuit MUST be prepared BEFORE your lab session or you may not have time to complete the experiment. Please submit your report and leave the lab by latest 10 minutes before the hour. …
Objectives:
In this experiment, you will design, connect and test a 3-bit Majority Logic Circuit. The design of this circuit MUST be prepared BEFORE your lab session or you may not have time to complete the experiment.
Please submit your report and leave the lab by latest 10 minutes before the hour.
IC chips:
The pin configurations for the chips are shown in step 5 below.
Introduction:
A 3-bit majority logic accepts three input bits. When the number of 1 among these input bits is more than the number of 0, we say that 1 is a majority. The 3-bit majority logic is to output TRUE (1) if 1 is a majority; otherwise it outputs FALSE (0).
Procedure:
A | B | C | F |
0 | 0 | 0 | |
0 | 0 | 1 | |
0 | 1 | 0 | |
0 | 1 | 1 | 1 |
1 | 0 | 0 | |
1 | 0 | 1 | |
1 | 1 | 0 | |
1 | 1 | 1 | |
F = m( _______________ )
F = M( _______________ )
B
A
C
Simplified SOP expression for F:
F = ____________________
for F above and write the simplified SOP expression for F.
the dot symbol (.) for the AND operation.
AY2019/20 Semester 2 – 1 of 2 – CS2100 Lab #7
Using 2-level AND-OR circuit | Using 2-level NAND circuit | ||
74LS00 | 74LS20 (partial) | ||||||||||||||
14 | 13 | 12 | 11 | 10 | 9 | 8 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | ||
Vcc | Vcc | ||||||||||||||
GND | GND | ||||||||||||
1 | 2 | 3 | 4 | 5 | 6 | 7 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
(If you encounter any problem with your circuit, use the logic probe to check it.)
Answer: How many more NAND gate(s) needed? ________
Marking Scheme: Report (18 marks), Circuit (7 marks); Total: 25 marks.
AY2019/20 Semester 2 – 2 of 2 – CS2100 Lab #7