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## Description

Objectives:

In this experiment, you will design, connect and test a 3-bit Majority Logic Circuit. The design of this circuit MUST be prepared BEFORE your lab session or you may not have time to complete the experiment.

Please submit your report and leave the lab by latest 10 minutes before the hour.

IC chips:

1. One 74LS00 chip (QUAD 2-input NAND gates)

2. One 74LS20 chip (DUAL 4-input NAND gates)

The pin configurations for the chips are shown in step 5 below.

Introduction:

A 3-bit majority logic accepts three input bits. When the number of 1 among these input bits is more than the number of 0, we say that 1 is a majority. The 3-bit majority logic is to output TRUE (1) if 1 is a majority; otherwise it outputs FALSE (0).

Procedure:

1. Complete the truth table below. The input bits are A, B and C. The output is F. For example, if ABC = 011, then F is 1.

 A B C F 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 0 1 0 1 1 1 0 1 1 1

F = m( _______________ )

F = M( _______________ ) B A    C

Simplified SOP expression for F:

F = ____________________

1. Write the sum-of-minterms expression in m notation and product-of-maxterms expression in M notation for F above.

1. Fill in the K-map Remember to write

for F above and write the simplified SOP expression for F.

the dot symbol (.) for the AND operation.

AY2019/20 Semester 2 – 1 of 2 – CS2100 Lab #7

1. Draw the logic diagrams to implement F in each of the following forms:

 Using 2-level AND-OR circuit Using 2-level NAND circuit
1. We will implement the circuit using NAND gates only. A useful step before constructing your circuit on the logic trainer is to plan the wiring. Draw your wiring plan below.  74LS00 74LS20 (partial) 14 13 12 11 10 9 8 14 13 12 11 10 9 8 Vcc Vcc GND GND 1 2 3 4 5 6 7 1 2 3 4 5 6 7
1. Construct your circuit on the logic trainer and show it to your Lab TA.

(If you encounter any problem with your circuit, use the logic probe to check it.)

1. How many more NAND gate(s), at the minimum, would you need if you want to turn the circuit into a 3-bit minority logic circuit? Call the output G. Draw the complete logic diagram below, with inputs A, B and C.

Answer: How many more NAND gate(s) needed? ________

Marking Scheme: Report (18 marks), Circuit (7 marks); Total: 25 marks.

AY2019/20 Semester 2 – 2 of 2 – CS2100 Lab #7