Logic Design of Digital Systems Solution

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Description

1 Lab assignment 1

In this assignment you will implement the results from problem set 2 in Verilog.

1.1 Five input adder

1.1(a). Using the FA module provided, generate the structural Verilog implementing the FA5 module as in pset 2 problem 1.1(a).

1.1(b). Using your FA5 module, generate the structural Verilog implementing the 4 bit ripple-carry adder as in pset

2 problem 1.2(c).

1.2 Maximum index

1.2(a). Using Verilog operators, generate the declarative Verilog implementing the MAM module as de ned in pset

2 section 2.3.

1.2(b). Using your MAM module, generate the structural Verilog implementing the maximum index function as in pset 2 problem 2.3(c).

1.3 Display

1.3(a). Using case statments, generate the procedural Verilog implementing the full ROM-based 7-segment display driver as in pset 2 section 3.1(b).

1.3(b). Using indexed assignments, generate the structural Verilog implementing the full mux-tree based 7-segment display driver as in pset 2 section 3.2(c)-(d).

1.H EE89 extra assignment

1.H(a). Synthesize the above modules using Vivado (Xilinx FPGA design environment).

1.H(b). Connect the 5-bit input of the display module to 5 of the switches on the board, and the output to a

7-segment display.

1.H(c). Compile and upload the designs to a Basys3 board and demonstrate their logic functionality to a TA.

Software: There are many different ways to run this. Details for each is provided in different sections below.

  1. Guides and resources: There are tons of guides on Verilog and all says basically the same thing

  1. Using EDA Playground

  • Log in: you can use your Google account to log in. This will enable you to save and download your work. If you choose, you can create a separate username but it is not necessary. This step is very important. Because this is a web interface, periodically, there can be a connection issue and an error such as “failed to connect to server” may appear. Refreshing will reconnect but you may lose your work if you do not have an account.
  • Settings:
  • LHS: Choose SystemVerilog/Verilog (we wont be using the SystemVerilog)

    • Don’t enable TL-Verilog, or any verification methodologies (OVM or UVM)
  • LHS: Choose Icarus Verilog 0.9.7

  • LHS: Run Option of “Open EPWave after run” will display the timing waveforms, and “Download files after run” will save your files locally (for submission).

  • Examples:Verilog/SystemVerilog contain a D flip-flop example design. Load that design (as shown above).
  • Convention in Verilog is to use at least 2 files, a testbench, and a design. The files are generally named with an extension of .v or a .sv. We will use .v in this class. To demark a testbench, we usually end the filename with .tb.

    • LHS: Select the dialog box: “Open EPWave after run”

    • TopLHS: Run the design by clicking on the “Run” button and a new window with the simulation result will pop up.

  • To use your own filenames instead of the provided “testbench.sv” and “design.sv”,
    • Locate Compile and Run Options

    • After –Wall, type in your complete filename such as dassign1_1.v and dassign1_1.tb.

    • The simulation will include those files (you can leave the testbench.sv and design.sv blank)

  1. Packaging the submission
  • Download your files
  • LHS: Select the dialog box: “Download files after run”

  • Make sure that your file names match the desired format for the submission for proper grading. The design assignments will contain the appropriate details.

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